\doxysubsubsection{Configuration\+\_\+section\+\_\+for\+\_\+\+CMSIS }
\hypertarget{group___configuration__section__for___c_m_s_i_s}{}\label{group___configuration__section__for___c_m_s_i_s}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_ga8eb40c0d30a09a0ae388e56b21d8f22c}{\+\_\+\+\_\+\+CM7\+\_\+\+REV}}~0x0110U
\begin{DoxyCompactList}\small\item\em Configuration of the Cortex-\/\+M7 Processor and Core Peripherals. \end{DoxyCompactList}\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_ga4127d1b31aaf336fab3d7329d117f448}{\+\_\+\+\_\+\+MPU\+\_\+\+PRESENT}}~1U
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\+\_\+\+\_\+\+NVIC\+\_\+\+PRIO\+\_\+\+BITS}}~4U
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gab58771b4ec03f9bdddc84770f7c95c68}{\+\_\+\+\_\+\+Vendor\+\_\+\+Sys\+Tick\+Config}}~0U
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gac1ba8a48ca926bddc88be9bfd7d42641}{\+\_\+\+\_\+\+FPU\+\_\+\+PRESENT}}~1U
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_ga3580fa1aeb7c2ed580904f8f70f8a919}{\+\_\+\+\_\+\+ICACHE\+\_\+\+PRESENT}}~1U
\item 
\#define \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_ga11d3ac679daeb58d0cec0a4e6ca59010}{\+\_\+\+\_\+\+DCACHE\+\_\+\+PRESENT}}~1U
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___configuration__section__for___c_m_s_i_s_doc-define-members}
\doxysubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___configuration__section__for___c_m_s_i_s_ga8eb40c0d30a09a0ae388e56b21d8f22c}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_CM7\_REV@{\_\_CM7\_REV}}
\index{\_\_CM7\_REV@{\_\_CM7\_REV}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_CM7\_REV}{\_\_CM7\_REV}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_ga8eb40c0d30a09a0ae388e56b21d8f22c} 
\#define \+\_\+\+\_\+\+CM7\+\_\+\+REV~0x0110U}



Configuration of the Cortex-\/\+M7 Processor and Core Peripherals. 

Cortex-\/\+M7 revision r1p2 \Hypertarget{group___configuration__section__for___c_m_s_i_s_ga11d3ac679daeb58d0cec0a4e6ca59010}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_DCACHE\_PRESENT@{\_\_DCACHE\_PRESENT}}
\index{\_\_DCACHE\_PRESENT@{\_\_DCACHE\_PRESENT}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_DCACHE\_PRESENT}{\_\_DCACHE\_PRESENT}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_ga11d3ac679daeb58d0cec0a4e6ca59010} 
\#define \+\_\+\+\_\+\+DCACHE\+\_\+\+PRESENT~1U}

CM7 data cache present Cortex-\/\+M7 processor and core peripherals \Hypertarget{group___configuration__section__for___c_m_s_i_s_gac1ba8a48ca926bddc88be9bfd7d42641}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_FPU\_PRESENT@{\_\_FPU\_PRESENT}}
\index{\_\_FPU\_PRESENT@{\_\_FPU\_PRESENT}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_FPU\_PRESENT}{\_\_FPU\_PRESENT}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_gac1ba8a48ca926bddc88be9bfd7d42641} 
\#define \+\_\+\+\_\+\+FPU\+\_\+\+PRESENT~1U}

FPU present \Hypertarget{group___configuration__section__for___c_m_s_i_s_ga3580fa1aeb7c2ed580904f8f70f8a919}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_ICACHE\_PRESENT@{\_\_ICACHE\_PRESENT}}
\index{\_\_ICACHE\_PRESENT@{\_\_ICACHE\_PRESENT}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_ICACHE\_PRESENT}{\_\_ICACHE\_PRESENT}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_ga3580fa1aeb7c2ed580904f8f70f8a919} 
\#define \+\_\+\+\_\+\+ICACHE\+\_\+\+PRESENT~1U}

CM7 instruction cache present \Hypertarget{group___configuration__section__for___c_m_s_i_s_ga4127d1b31aaf336fab3d7329d117f448}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_MPU\_PRESENT@{\_\_MPU\_PRESENT}}
\index{\_\_MPU\_PRESENT@{\_\_MPU\_PRESENT}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_MPU\_PRESENT}{\_\_MPU\_PRESENT}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_ga4127d1b31aaf336fab3d7329d117f448} 
\#define \+\_\+\+\_\+\+MPU\+\_\+\+PRESENT~1U}

CM7 provides an MPU \Hypertarget{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_NVIC\_PRIO\_BITS@{\_\_NVIC\_PRIO\_BITS}}
\index{\_\_NVIC\_PRIO\_BITS@{\_\_NVIC\_PRIO\_BITS}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_NVIC\_PRIO\_BITS}{\_\_NVIC\_PRIO\_BITS}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460} 
\#define \+\_\+\+\_\+\+NVIC\+\_\+\+PRIO\+\_\+\+BITS~4U}

CM7 uses 4 Bits for the Priority Levels \Hypertarget{group___configuration__section__for___c_m_s_i_s_gab58771b4ec03f9bdddc84770f7c95c68}\index{Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}!\_\_Vendor\_SysTickConfig@{\_\_Vendor\_SysTickConfig}}
\index{\_\_Vendor\_SysTickConfig@{\_\_Vendor\_SysTickConfig}!Configuration\_section\_for\_CMSIS@{Configuration\_section\_for\_CMSIS}}
\doxysubsubsubsubsection{\texorpdfstring{\_\_Vendor\_SysTickConfig}{\_\_Vendor\_SysTickConfig}}
{\footnotesize\ttfamily \label{group___configuration__section__for___c_m_s_i_s_gab58771b4ec03f9bdddc84770f7c95c68} 
\#define \+\_\+\+\_\+\+Vendor\+\_\+\+Sys\+Tick\+Config~0U}

Set to 1 if different Sys\+Tick Config is used 